Compare the different types of hardware description languages

System Engineering

As digital systems are becoming more complex, more computer-aided design (CAD) tools are introduced into hardware design process. The traditional paper-and-pencil design have been replaced by the modern design entry, verification, and automatic hardware generation tools. Hardware Description Language (HDL) is a latest addition to this design methodology. Many new CAD tools have been developed based on HDLs to simplify the process of digital system design. HDL is a language to decribe hardware. It can be used for simulation, modeling, testing, design, and documentation. This language is used for formal description of functional and wiring details of digital systems.

Available HDLs software are functioning as simulators and hardware synthesis programs. A simulation program is designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides design verification. HDLs give an illusion of being software programming languages, but it should be classified as specification languages or modeling languages. HDLs also include an explicit notion of time, which make it as an hardware languages.

The list in Table 1 below shows the existing hardware description languages for digital system.

Abbreviation

Name

Notice

ABEL

Advanced Boolean Expression Language

AHDL

Altera HDL

a proprietary language from Altera

AHPL

A Hardware

Programing language

Abbreviation

Name

Notice

Bluespec

high-level HDL originally based on Haskell, now with a SystemVerilog syntax

C-to-Verilog

Converter from C to Verilog

CDL

Computer Design Language

Developed in academic environment

Confluence

a functional HDL; has been discontinued

CONLAN

Consensus Language

CoWareC

a C-based HDL by CoWare. Now discontinued in favour of SystemC

CUPL

a proprietary language from Logical Devices, Inc.

ELLA

no longer in common use

Handel-C

a C-like design language

HJJ

Hardware Join Java

based on Join Java

HML

based on SML

Hydra

based on Haskell

IDL

Interactive Design Language

Internal IBM language

Impulse C

another C-like HDL

ParC

Parallel C++

C++ extended with HDL style threading and communication for task-parallel programming

JHDL

based on Java

Lava

based on Haskell

Lola

a simple language used for teaching

M

A HDL from Mentor Graphics

MyHDL

based on Python

PALASM

for Programmable Array Logic (PAL) devices

ROCCC 2.0

Riverside Optimizing Compiler for Configurable Computing

Free and open source C to HDL tool

RHDL

based on the Ruby programming language

Ruby (hardware description language)

SystemC

a standardized class of C++ libraries for high-level behavioral and transaction modeling of digital hardware at a high level of abstraction, i.e. system-level

SystemVerilog

a superset of Verilog, with enhancements to address system-level design and verification

SystemTCL

SDL based on Tcl.

TDL

TEGAS Description Language

TEGAS (Test Generation and Simulation)

Abbreviation

Name

Notice

TI-HDL

Texas Instruments HDL

Verilog

most widely-used and well-supported HDL

VHDL

VHSIC HDL

most widely-used and well-supported HDL

ZEUS

Nonprocedural language created at General Electric Corporation

Table 1 modified from [2]

There are many existing hardware description languages but let focus our discussion on the Verilog and VHDL as they are two most major hardware description languages (HDLs) used by hardware designers in industry.

VHDL(VHSIC Hardware Description Language) begins with the request of standard design and documentation tool for the Very High Speed Integrated Circuits (VHSIC) program and a workshop sponsored by the U.S. Department of Defense was started in 1981. VHDL 2.0 was released under a contract with IEM, Texas Instruments, and Intermatrics. VHDL undergoes further development and standardization, and finally made an IEEE standard in 1987. Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 at Automated Integrated Design Systems (renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. [4]

Verilog HDL is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits. VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

It is well-known that Verilog is based on C programming and VHDL is based on Ada programming. It means that Verilog is weak typing, whereas VHDL is strongly typed. Weak typing allows a value of one type to be treated as another, for instance, characters can be used as integers. It is sometime useful, but some kinds of program faults may be undetected at compile time and even at runtime. Strong typing is safe. Any operation performs on the wrong type of value raises an error.

Now, let move on our discussion on the language features in VHDL and Verilog.

module module_name (input and output ports);

physical and other parameters.

declarations.

module_item.

endmodule

ENTITY component_name IS

input and output ports.

physical and other parameters.

END component_name;

--

ARCHITECTURE identifier OF component_name IS

declarations.

BEGIN

component_item.

END identifier;

1

Figure 1 Description of component in VHDL Figure 2 Description of component in Verilog

The description of component in VHDL consists of an interface specification and an architecture specification as shown in figure 1, whereas Verilog only one part which is the module as shown in figure 2. The interface description in VHDL begin with the ENTITY keyword and followed by the name of component, IS which is also a VHDL keyword, and the input-output ports of the component. Other parameters such as time dependencies can also be included in this part. The architecture specification begins with the ARCHITECTURE keyword which decribes the functionality of the component. A functional description is start after the BEGIN keyword. For Verilog, the description of component begins with the module keyword and end with a endmodule, which is also a keyword in Verilog. The heading of the description of component for Verilog-2001 includes the name of the module and the input-output ports in brackets. VHDL is case insensitive, but it use uppercase letters for all keywords here for clarification. Verilog is case sensitive, so all keywords are in lowercase letters.

ENTITY mylogic IS

PORT ( W, X : IN BIT;

Y : OUT BIT;

Z : OUT BIT_VECTOR (7 DOWNTO 0));

END mylogic;

--

ARCHITECTURE ...

module mylogic (

input W, X,

output Y,

output reg [7:0] Z

);

...

endmoduleFirst, we move on to the port declaration for both HDLs.

Figure 3: Port declaration in VHDL Figure 4: Port declaration in Verilog

VHDL code in figure 3 and Verilog-2001 code in figure 4 is equvailent code to declare ports. The port declaration for VHDL is put inside the interface specification, whereas the port declaration for Verilog is at the beginning of an module. For VHDL, the name of component comes after the ENTITY keyword and is followed by IS keyword. The next line begins with PORT keyword with the name of the ports in parentheses. The two inputs of mylogic are W and X, and the outputs are Y and a 8-bits vector, Z. The keywords IN and OUT specify the mode of the port signal, and type BIT and BIT_VECTOR are part of the standard package in VHDL. For Verilog-2001, all the port declaration is inside a bracket after the name of module, mylogic. The input-output ports are by default wire data type. The reg variable store the last value that was procedurally assigned to them whereas wire variable is net data type that represent the physical connection between components. The data type in VHDL that identity to reg and wire are variable and signal repectively. Code in Verilog looks simplier and computer engineers prefer C-like Verilog than Ada-like VHDL as most of them learn C programming in their course programme.

module flop (

input reset, din, clk,

output reg qout

);

always @ (negedge clk)

begin

if (reset)

#1 qout <= 1’b0;

else

#1 qout <= din;

end

endmodule

ENTITY flop IS

GENERIC (td_reset, td_in : TIME := 8NS);

PORT ( reset, din, clk : IN BIT;

qout : BUFFER BIT := ‘0’);

END flop;

--

ARCHITECTURE behavioural OF flop IS

BEGIN

PROCESS (clk)

BEGIN

IF (clk =’0’ AND clk’EVENT) THEN

IF reset = ‘1’ THEN

qout <= ‘0’ AFTER td_reset;

ELSE

qout <= din AFTER td_in;

END IF;

END IF;

END PROCESS;

END behavioral;

Figure 5: VHDL model of flip-flop [6] p.45 Figure 6: Verilog-2001 model of flip-flop

The codes in figure 5 and figure 6 are equivalent code in VHDL and Verilog describing a synchronous falling-edge D-type flip-flop. In VHDL, the interface description in the upper part specifies the name of component as flop, and is followed by the GENERIC keyword with the name of a model timing parameter in parentheses. The two timing parameter, td_reset and td_in are of type TIME and have a default value of 8 NS. Verilog does not need a special declaration for time delay. It uses #1 in the code to indicate a delay of 1 time unit. The time unit is depends on the internal clock of simulator used. To generate an identity case for code in figure 5 and figure 6, 1 unit time is assumed to be 8NS. VHDL code in figure 5 use PROCESS keyword initials a process statement for bodying sequential statements whereas Verilog use always @... to start a procedural block that execute procedures in parallel. VHDL has if-then-else statement with an end if, but Verilog only need if-else statement. The process statement in VHDL has an if-statement with a clk =’0’ AND clk’EVENT condition where the condition becomes true when the falling edge of clk is observed. It has the same function with always @ (negedge clk) in figure 6. The last highlight for this example is the symbol in VHDL, := which used for variable assignments, whereas <= used for assignments into signals. For Verilog, <= is used for non-blocking assignments.

C1

1D

1R

Q

enable

din

clock

dff_in

reset

qout

S1

1D

~1D

Figure 7: Hardware realization of der_flop [6] p.58

module der_flop (

input din, reset, enable, clk,

output reg qout

);

wire dff_in;

mux2_1 mx (enable, din, qout, dff_in);

flop ff ( reset, dff_in, clk, qout);

endmodule

module flop(

...

endmodule

module mux2_1(

...

endmodule

ENTITY der_flop IS

PORT ( din, reset, enable, clk : IN BIT;

qout : BUFFER BIT := ‘0’);

END der_flop;

--

ARCHITECTURE behavioural OF der_flop IS

COMPONENT flop IS

GENERIC (td_reset, td_in : TIME := 8NS);

PORT ( reset, din, clk : IN BIT;

qout : BUFFER BIT);

END COMPONENT;

COMPONENT mux2_1 IS

GENERIC (dz_delay : TIME := 6NS);

PORT ( sel, data1, data0 : IN BIT;

z : OUT BIT);

END COMPONENT;

SIGNAL dff_in : BIT;

BEGIN

mx : mux2_1 PORT MAP (enable, din, qout, dff_in);

ff : flop PORT MAP (reset, dff_in, clk, qout);

END behavioral;

Figure 8: Structural description of der_flop in VHDL Figure 9: der_flop in Verilog

The hardware realization of der_flop in figure 7 clearly shows that the flip-flop, der_flop is a combination of a 2-to-1 multiplexer, mux2_1 and a type D flip-flop, flop. The component instantiation used in VHDL is identical to the module instantiation in Verilog. The VHDL architecture body in figure 8 can be divided into two parts, which are the architecture declaration part and architecture statement part. The architecture declaration part consists of component declaration and signal declaration. The architecture statement part consists of a component instantiation statement. Component declaration part starts with COMPONENT keyword, followed by the name and input-output ports of component being instantiated. The keyword SIGNAL begins the signal declaration and it is used as intermediate signal in the der_flop architecture. Verilog declare this intermediate signal, dff_in as net data type, wire. All component instantiations and module instantiations are concurrent, so the order is not important. Based on the 2-to-1 multiplexer instanced, component instantiation statement in VHDL includes a label (mx), component name (mux2_1), PORT MAP keyword, and assocoation between the actual signals that are visible in the architecture body of der_flop and the ports of component being instantiated(enable, din, qout, dff_in). The module instantiation in Verilog is similar to the component instantiation statement, but it begins with the name of module, followed by an identifier, and the association list which the list in in same order as the port list in the module defination. Let us take the 2-to-1 multiplexer instantiation as an example, the association list enable, din, qout, dff_in are corresponding to reset, din, clk, qout in the port list of mux2_1.

There are still many other different features exist between VHDL and Verilog. A summary is done on the equivalent keyword in VHDL and Verilog in Table 2. The keywords in VHDL or Verilog are in bold type and names of user-defined objects are in italics.

Verilog/VHDL equivalent keywords

Keyword

Equivalent

Verilog

VHDL

abs.vhd

?: // expression needed

out1 = (in1 < 0) ? -in1 : in1;

out1 <= abs(in1);

access.vhd

// no counterpart

// no counterpart

type pointer is access memory;

after.vhd

#

#10 out1 = in1;

out1 <= in1 after 10 ns;

alias.vhd

`define

`define status word[13]

alias status : std_logic is word(13);

all.vhd

+lib ...

// command line option

use libname.pkgname.all;

always.v

process

always begin ... end

process begin ... end process;

and.v // gate

vitaland

and (out1, in1, in2);

vitaland(out1, in1, in2);

and.vhd

&, &&

out1 = in1 & in2;

out1 <= in1 and in2;

architecture.vhd

module

module name; endmodule

architecture name of entityname is ... end name;

array.vhd

reg[range] memory [range]

reg[0:3] memory [0:7]

type memory is array(0 to 3) of std_logic_vector(0 to 7);

assert.vhd

$display

if (not condition) $display("string");

assert condition report "string" severity level;

assign.v

when ... else

if ... assign out1 = 0; else deassign out1;

when ... out1 <= '0'; else out1 <= 'Z';

attribute.vhd

// no counterpart

// no counterpart

attribute capacitance : farads;

begin.v

begin

begin multiple statements end

name begin ... end name;

begin.vhd

begin

begin multiple statements end

name begin ... end name;

block.vhd

begin ... end

begin multiple statements end

alu : block ... end block alu;

body.vhd

// hierarchical path names

pkgname.definitions

package body pkgname is ... end pkgname;

buf.v // gate

vitalbuf

buf (out1, in1);

vitalbuf(out1, in1);

buffer.vhd

out

out out1;

port(out1 : buffer std_logic);

bufif0.v // gate

vitalbufif0

bufif0(out1, in1, control1);

vitalbufif0(out1, in1, control1);

bufif1.v // gate

vitalbufif1

bufif1(out1, in1, control1);

vitalbufif1(out1, in1, control1);

bus.vhd

tri

tri name;

signal name : std_logic bus;

case.v

case

case (expression) choices endcase

case expression is when choice => out1 <= in1; end case;

case.vhd

case

case (expression) choices endcase

case expression is when choice => out1 <= in1; end case;

casex.v

­ no direct counterpart

casex (expression) choices endcase

­ no direct counterpart

casez.v

­ no direct counterpart

casez (expression) choices endcase

­ no direct counterpart

cmos.v // gate

­ no standard counterpart

cmos(out1, in1, ncontrol, pcontrol);

­ no standard counterpart

component.vhd

// structural instantiation

inverter u1 (out1, in1);

componentinverter port(out1 : out std_logic; in1 : in std_logic);

configuration.vhd

// no counterpart

// no counterpart

configuration name of EntityName is ... end name;

constant.vhd

parameter

parameter maxsize = 64;

constant maxsize : positive := 64;

deassign.v

when ... else

if ... assign out1 = 0; else deassign out1;

when ... out1 <= '0'; else out1 <= 'Z';

default.v

others

case (expression) ... default : out1 = in2;

case expression is ... when others => out1 <= in2; end case;

defparam.v

generic map

defparam maxsize = 32;

generic map(maxsize => 32);

disable.v

exit, next, return

for ... disable name ...

loop ... next when ... end loop;

disconnect.vhd

?: // expression needed

out1 = guard ? in1 : 'bz;

disconnect GuardedSignalName : std_logic after 10 ns;

downto.vhd

// [higher:lower]

[15:0]

(15 downto 0)

else.v

else

if ... else if ... else

if ... then ... elsif ... then ... else ... end if;

else.vhd

else

if ... else if ... else

if ... then ... elsif ... then ... else ... end if;

elsif.vhd

else, if

if ... else if ... else

if ... then ... elsif ... then ... else ... end if;

end.v

end

begin multiple statements end

... end ... ;

end.vhd

end

begin multiple statements end

... end ... ;

endcase.v

case ... end case;

case (expression) choices endcase

case expression is when choice => out1 <= in1; end case;

endfunction.v

function ... end;

function name; ... endfunction

function name(...) return std_logic is ... end name;

endmodule.v

entity/architecture

module name; ... endmodule

entity name is ... end name; architecture ...

endprimitive.v // gate

VitalTruthTable

primitive name ... endprimitive

procedure VitalTruthTable(...);

endspecify.v

generic

specify specparem setup=10; endspecify

entity name is generic(setup : time := 10 ns); ...

endtable.v // gate

VitalTruthTable

table ... endtable

procedure VitalTruthTable(...);

endtask.v

procedure ... end;

task name; ... endtask

procedure name(...) is ... end name;

entity.vhd

module

module name; ... endmodule

entity name is ... end name;

event.v

signal

event name;

signal name : sync_type;

exit.vhd

disable

for ... disable name ...

loop ... exit when ... end loop;

file.vhd

$input

$input("source.txt");

file source_code : text is in "source.txt";

for.v

for

for (i = 1; i <= 10; i = i + 1)

for i in 1 to 10 loop

for.vhd

for, repeat

for (i = 1; i <= 10; i = i + 1)

for i in 1 to 10 loop

force.v

­ user defined resolution function

if ... force out1 = 0; else release out1;

out1 <= stomp_value; ­ perhaps in an error_injector component.

forever.v

wait

forever @(posedge clock) out1 = in1;

wait until rising_edge(clock); out1 <= in1;

fork.v

­ user defined synchronization

... fork concurrent_execution join ...

wait on sync'transaction until sync = 300;

function.v

function

function name; ... endfunction

function name(...) return std_logic is ... end name;

function.vhd

function

function name; ... endfunction

function name(...) return std_logic is ... end name;

generate.vhd

// no counterpart

// no counterpart

generate_label : if expression generate ... end generate;

generic.vhd

defparam, specparem

defparam maxsize = 32;

entity name is generic(maxsize : natural := 32); ...

group.vhd

// no counterpart

// no counterpart

attribute rising_delay of c2q : group is 7.2 ns;

guarded.vhd

?: // expression needed

out1 = guard ? in1 : 'bz;

block (guard-expression) ... out1 <= guarded in1 after 10 ns;

highz0.v // strength

'Z' in std_logic_1164

buf(highz0) out1;

out1 <= 'Z';

highz1.v // strength

'Z' in std_logic_1164

buf(highz1) out1;

out1 <= 'Z';

if.v

if

if ... else if ... else

if ... then ... elsif ... then ... else ... end if;

if.vhd

if

if ... else if ... else

if ... then ... elsif ... then ... else ... end if;

impure.vhd

// no counterpart

// no counterpart

impure function ...

in.vhd

input

output out1; input in1;

port(out1 : out std_logic; in1 : in std_logic);

inertial.vhd

// inertial by default

#10 out1 = in1;

out1 <= reject 5 ns inertial in1 after 10 ns;

initial.v

process

initial begin ... end

process begin ... wait; end process;

inout.v

inout

inout inout1;

port(inout1 : inout std_logic);

inout.vhd

inout

inout inout1;

port(inout1 : inout std_logic);

input.v

in

output out1; input in1;

port(out1 : out std_logic; in1 : in std_logic);

integer.v

­ predefined type

integer name;

signal name : integer;

is.vhd

// unnecessary

module name; ... endmodule

entity name is ... end name;

join.v

­ user defined synchronization

... fork concurrent_execution join ...

wait on sync'transaction until sync = 300;

label.vhd

// no counterpart

// no counterpart

attribute location of adder1 : label is (10, 15);

large.v // charge

­ enumerated type

trireg(large) out1;

type strength is (small, medium, large);

library.vhd

+lib ...

// command line option

library libname;

linkage.vhd

// no counterpart

// no counterpart

port(out1 : linkage std_logic; in1 : in std_logic);

literal.vhd

// no counterpart

// no counterpart

attribute areaof others : literal is 7;

loop.vhd

while, for, etc.

while (condition)

while (condition) loop

macromodule.v // gate

entity/architecture

macromodule name; ... endmodule

entity name is ... end name; architecture ...

map.vhd

// structural instantiation

inverter u1 (out1, in1);

u1 : inverter port map(out1 => out1, in1 => in1);

medium.v // charge

­ enumerated type

trireg(medium) out1;

type strength is (small, medium, large);

mod.vhd

%

out1 = in1 % in2;

out1 <= in1 mod in2;

module.v

entity/architecture

module name; ... endmodule

entity name is ... end name; architecture ...

nand.v // gate

vitalnand

nand (out1, in1, in2);

vitalnand(out1, in1, in2);

nand.vhd

~, &

out1 = ~(in1 & in2);

out1 <= in1 nand in2;

negedge.v

falling_edge ­ std_logic_1164

always @ (negedge clk) begin ... end

wait until falling_edge(clk);

new.vhd

// no counterpart

// no counterpart

pointer := new name ... deallocate(name);

next.vhd

disable

for ... disable name ...

loop ... next when ... end loop;

nmos.v // gate

vitalbufif1

nmos(out1, in1, control1);

vitalbufif1(out1, in1, control1, ... ResultMap);

nor.v // gate

vitalnor

nor (out1, in1, in2);

vitalnor(out1, in1, in2);

nor.vhd

~, |

out1 = ~(in1 | in2);

out1 <= in1 nor in2;

not.v // gate

vitalinv

not (out1, in1);

vitalinv(out1, in1);

not.vhd

~

out1 = ~in1;

out1 <= not(in1);

notif0.v // gate

vitalinvif0

notif0(out1, in1, control1);

vitalinvif0(out1, in1, control1);

notif1.v // gate

vitalinvif1

notif1(out1, in1, control1);

vitalinvif1(out1, in1, control1);

null.vhd

// no direct counterpart

// no direct counterpart

case expression is when choice => out1 <= null; end case;

of.vhd

// unnecessary

module name; ... endmodule

architecture name of entityname is ... end name;

on.vhd

@

@(posedge in1) ...

wait on in1;

open.vhd

// no counterpart

// no counterpart

u1 : inverter port map(out1 => open, in1 => in1);

or.v // gate

vitalor

or (out1, in1, in2);

vitalor(out1, in1, in2);

or.vhd

|, ||

out1 = in1 | in2;

out1 <= in2 or in2;

others.vhd

default

case (expression) ... default : out1 = in2;

case expression is ... when others => out1 <= in2; end case;

out.vhd

output

output out1; input in1;

port(out1 : out std_logic; in1 : in std_logic);

output.v

out

output out1; input in1;

port(out1 : out std_logic; in1 : in std_logic);

package.vhd

// hierarchical path names

pkgname.definitions

package pkgname is ... end pkgname;

parameter.v

constant

parameter maxsize = 64;

constant maxsize : positive := 64;

pmos.v // gate

vitalbufif0

pmos(out1, in1, control1);

vitalbufif0(out1, in1, control1, ... ResultMap);

port.vhd

module name (port signals);

module name (out1, in1); ... endmodule

port(out1 : out std_logic; in1 : in std_logic);

posedge.v

rising_edge ­ std_logic_1164

always @ (posedge clk) begin ... end

wait until rising_edge(clk);

postponed.vhd

#0

#0 ...

postponed process ...

primitive.v // gate

VitalTruthTable

primitive name ... endprimitive

procedure VitalTruthTable(...);

procedure.vhd

task

task name; ... endtask

procedure name(...) is ... end name;

process.vhd

always

always begin ... end

process begin ... end process;

pull0.v // strength

'L' in std_logic_1164

buf(pull0) out1;

out1 <= 'L';

pull1.v // strength

'H' in std_logic_1164

buf(pull1) out1;

out1 <= 'H';

pulldown.v // gate

vitalbuf

pulldown(pull0) (out1);

out1 <= 'L';

pullup.v // gate

vitalbuf

pullup(pull1) (out1);

out1 <= 'H';

pure.vhd

// no counterpart

// no counterpart

pure function ...

range.vhd

// no counterpart

// no counterpart

for i in inputs'range loop ... end loop;

rcmos.v // gate

­ no standard counterpart

rcmos(out1, in1, ncontrol, pcontrol);

­ no standard counterpart

record.vhd

// hierarchical path names

module record_name ... endmodule

type name is record ... end record;

reg.v

variable, signal

reg name;

variable name : std_logic;

register.vhd

trireg

trireg name;

signal name: std_logic register;

reject.vhd

// no counterpart

// no counterpart

out1 <= reject 5 ns inertial in1 after 10 ns;

release.v

­ user defined resolution function

if ... force out1 = 0; else release out1;

out1 <= stomp_value; ­ perhaps in an error_injector component.

rem.vhd

%

out1 = in1 % in2;

out1 <= in1 rem in2;

repeat.v

for

repeat (10)

for i in 1 to 10 loop ...

report.vhd

$display

if (not condition) $display("string");

assert condition report "string" severity level;

return.vhd

disable

task name; ... disable name;

function name(...) return std_logic is ... end name;

rnmos.v // gate

vitalbufif1

rnmos(out1, in1, control1);

vitalbufif1(out1, in1, control1, ... ResultMap);

rol.vhd

{} // expression needed

alu_data = {alu_data[5:0], alu_data[7:6]};

alu_data <= alu_data rol 2;

ror.vhd

{} // expression needed

alu_data = {alu_data[1:0], alu_data[7:2]};

alu_data <= alu_data ror 2;

rpmos.v // gate

vitalbufif0

rpmos(out1, in1, control1);

vitalbufif0(out1, in1, control1, ... ResultMap);

rtran.v // gate

­ no standard counterpart

rtran(inout1, inout2);

­ no standard counterpart

rtranif0.v // gate

­ no standard counterpart

rtranif0(inout1, inout2, control);

­ no standard counterpart

rtranif1.v // gate

­ no standard counterpart

rtranif1(inout1, inout2, control);

­ no standard counterpart

scalared.v

std_logic_vector

tri1 scalared[63:0] name;

signal name : std_logic_vector(63 downto 0);

select.vhd

?: // expression needed

cond_expr ? true_expr : false_expr

with expression select choices

severity.vhd

$stop, $finish

$stop(1);

assert condition report "string" severity level;

shared.vhd

// no counterpart

// no counterpart

shared variable ...

signal.vhd

wire

wire in1;

signal in1 : std_logic;

sla.vhd

// sla function needed

alu_data = sla(alu_data, 2);

alu_data <= alu_data sla 2;

sll.vhd

<<

alu_data = alu_data << 2;

alu_data <= alu_data sll 2;

small.v // charge

­ enumerated type

trireg(small) out1;

type strength is (small, medium, large);

specify.v

generic

specify specparem setup=10; endspecify

entity name is generic(setup : time := 10 ns); ...

specparam.v

generic

specify specparem setup=10; endspecify

entity name is generic(setup : time := 10 ns); ...

sra.vhd

// sra function needed

alu_data = sra(alu_data, 2);

alu_data <= alu_data sra 2;

srl.vhd

>>

alu_data = alu_data >> 2;

alu_data <= alu_data srl 2;

strong0.v // strength

'0' in std_logic_1164

buf(strong0) out1;

out1 <= '0';

strong1.v // strength

'1' in std_logic_1164

buf(strong1) out1;

out1 <= '1';

subtype.vhd

// predefined types

// predefined types

subtype subtypename is typename range ... ;

supply0.v // strength

'0' in std_logic_1164

buf(supply0) out1;

out1 <= '0';

supply1.v // strength

'1' in std_logic_1164

buf(supply1) out1;

out1 <= '1';

table.v // gate

VitalTruthTable

table ... endtable

procedure VitalTruthTable(...);

task.v

procedure

task name; ... endtask

procedure name is ... end name;

then.vhd

// unnecessary

if ... else if ... else

if ... then ... elsif ... then ... else ... end if;

time.v

­ predefined type

time setup;

generic(setup: time := 3 ns);

to.vhd

// [lower:higher]

[0:15]

(0 to 15)

tran.v // gate

­ no standard counterpart

tran(inout1, inout2);

­ no standard counterpart

tranif0.v // gate

­ no standard counterpart

tranif0(inout1, inout2, control);

­ no standard counterpart

tranif1.v // gate

­ no standard counterpart

tranif1(inout1, inout2, control);

­ no standard counterpart

transport.vhd

// inertial only

// no counterpart

out1 <= transport in1 after 10 ns;

tri.v // net

bus, ­ resolved signal

tri out1;

signal out1 : resolved_tri;

tri0.v // net

­ resolved signal

tri0 out1;

signal out1 : resolved_tri0;

tri1.v // net

­ resolved signal

tri1 out1;

signal out1 : resolved_tri1;

triand.v // net

­ resolved signal

triand out1;

signal out1 : resolved_triand;

trior.v // net

­ resolved signal

trior out1;

signal out1 : resolved_trior;

trireg.v // net

register, ­ resolved signal

trireg out1;

signal out1 : resolved_trireg;

type.vhd

// predefined types

// predefined types

type typename ... enumerate;

unaffected.vhd

?: // expression needed

#delay_value out1 = condition ? out1 : in1;

out1 <= unaffected when condition else in1 after delay_value;

units.vhd

// no counterpart

// no counterpart

physical type ... units ...

until.vhd

wait

wait (condition);

wait until condition;

use.vhd

+lib ...

// command line option

use libname.pkgname.all;

variable.vhd

reg

reg name;

variable name : std_logic;

vectored.v

­ enumerated type

tri vectored[31:0] name;

signal name : enumerated_type;

wait.v

wait

wait (condition);

wait [on] [until] [for] ... ;

wait.vhd

wait

wait (condition);

wait [on] [until] [for] ... ;

wand.v // net

­ resolved signal

wand out1;

signal out1 : resolved_wand;

weak0.v // strength

'L' in std_logic_1164

buf(weak0) out1;

out1 <= 'L';

weak1.v // strength

'H' in std_logic_1164

buf(weak1) out1;

out1 <= 'H';

when.vhd

case

case (expression) choices

case expression is when choice => out1 <= in1; end case;

while.v

while

while (condition)

while (condition) loop

while.vhd

while

while (condition)

while (condition) loop

wire.v // net

­ resolved signal

wire out1;

signal out1 : resolved_wire;

with.vhd

?: // expression needed

cond_expr ? true_expr : false_expr

with expression select choices

wor.v // net

­ resolved signal

wor out1;

signal out1 : resolved_wor;

xnor.v // gate

vitalxnor

xnor (out1, in1, in2);

vitalxnor(out1, in1, in2);

xnor.vhd

^~

out1 = in1 ^~ in2;

out1 <= in1 xnor in2;

xor.v // gate

vitalxor

xor (out1, in1, in2);

vitalxor(out1, in1, in2);

xor.vhd

^

out1 = in1 ^ in2;

out1 <= in1 xor in2;Table 2 [1]

Conclusion

This case study began with the introduction of the Hardware Description Languages (HDLs). Then it focused the discussion on the two major HDLs which are VHDL and Verilog. The discussion began with the brief history of VHDL and Verilog, followed by comparing the common application industry for both languages. As VHDL and Verilog are based on different programming languages, the different syntax and semantics for theses two languages are also discussed. Then the discussion moved on comparing the elements of both languages. Identical codes for VHDL and Verilog were used for comparison. At last, a summarised table for the equivalent keywords in VHDL and Verilog were attached for reference. As conclusion, VHDL and Verilog have same concept as both of them are hardware description languages for the purpose of simulation, modelling, testing, design, and documentation. They are different from the aspects of the language elements, assignments, declarations, statements, operators, and etc.